Understanding SR Latches: Complete Guide to Set-Reset Latch, Gated & Clocked Versions

An SR (Set-Reset) latch is a fundamental sequential logic circuit capable of storing one bit of information. At its core, the basic latch uses cross-coupled logic gates—either NOR or NAND gates—where the output of one gate feeds back into the input of the other. This feedback loop creates a memory effect that holds the circuit's state indefinitely even after the input triggers are removed. When you press the button connected to the 'Set' input, the circuit forces the main output to a high state (logic 1), illuminating the LED to show that a state has been stored. Conversely, triggering the 'Reset' input forces the output back to a low state (logic 0), turning the LED off. Gated and clocked variants introduce an extra enable or clock signal, ensuring the latch only responds to Set and Reset inputs when the control signal is actively pulsed, allowing for synchronized operation in digital systems.